Numerous electronic equipment having only one input voltage of a low level use a voltage converter with which an output voltage of a higher amplitude can be generated. Particularly, voltage doublers are currently used for multiplying the amplitude of the input voltage by two.
FIG. 1 shows a prior-art voltage converter referred to as “switched capacity” converter. This is a voltage doubler.
This voltage converter uses four transistors T1-T2-T3-T4 functioning as switches, as well as a capacitance Cp. The transistors T2 and T3 are closed at the high levels of the clock signal CLK, while the transistors T1 and T4 are closed at the low levels of the clock signal CLK via the inverter INV.
When T2 and T3 are equivalent to closed switches, the capacitance Cp is charged until it has a potential difference Ucp=VDD at its terminals. When T1 and T4 are, in their turn, equivalent to closed switches, the terminal N1 is connected to the input voltage VDD which, taking the charge state of the capacitance Cp into account, brings the output terminal Vout to the potential 2*VDD.
The capacitance Cr does not have an important role for the function of the converter but allows a reduction of the ripple of the output voltage.
This type of voltage converter has a certain number of limitations when the level of the input voltage varies from one electronic apparatus to another.
At different switching instants of the switches T2–T3 and T1–T4, the capacitance Cp is charged with a time constant which is defined by the resistances of the drain-source junctions of the transistors T2–T3 and T1–T4. The peaks of the switching current Ic at different switching instants are therefore proportional to the input voltage VDD and inversely proportional to the resistance of the drain-source RMOS of the transistors T2–T3 and T1–T4. The switching current Ic thus has the form of:Ic=K1.VDD/RMOS with K1=constant  Eq. 1Moreover, when they are equivalent to closed switches, the resistance RMOS of the transistors T1-T2-T3-T4 of the MOS type is inversely proportional to their gate-source voltage, i.e. inversely proportional to the input voltage VDD when they are equivalent to closed switches when a potential difference VGS0 of the amplitude VDD is applied between their gate and their source via the signal CLK. The resistance RMOS of each transistor T1-T2-T3-T4 is thus in the form of:RMOS=K2/VGS0 with K2=constant  Eq. 2RMOS=K2/VDDWhile taking Eq. 1 into account, the switching current Ic increases in a quadratic manner as a function of the input voltage VDD. Consequently, it has the form of:Ic=K3.VDD2 with K3=constant  Eq. 3
These switching current peaks generate parasitic noise which is stronger as the amplitude of the peaks is higher. Particularly if the input voltage VDD increases from electronic equipment to electronic equipment, the parasitic noise also increases. Taking into account that the current Ic increases in a quadratic manner as a function of the input voltage VDD, a small variation of the input voltage VDD involves a considerable variation of the switching current and thus of the parasitic noise.
With such a voltage converter, the noise level can therefore not be guaranteed at a constant level when the input voltage VDD varies, even if VDD varies only very slightly. This technical limitation of such a prior-art converter is particularly annoying for satisfying the requirements of electromagnetic compatibility standards.